DocumentCode :
3251929
Title :
Evaluation of power efficient adder and multiplier circuits for FPGA based DSP applications
Author :
Bhattacharjee, Subhankar ; Sil, Sanjib ; Basak, Biswajit ; Chakrabarti, Amlan
Author_Institution :
Dept.-ECE, Techno India Coll. of Technol., Kolkata, India
fYear :
2011
fDate :
26-28 Dec. 2011
Firstpage :
1
Lastpage :
5
Abstract :
This paper describes the design and implementation of low power arithmetic circuits for digital signal processing (DSP) applications, using Xilinx XC5VLX30 (Virtex-5) field programmable gate array (FPGA) devices. DSP is a highly demanding application domain in the present day technology wherein the demands for enhanced performance and reduced resource utilization have increased over the years. Recent advancements in FPGA design technology through the incorporation of DSP functional blocks along with the inherent FPGA features like high flexibility through reconfiguration, reusability, moderate cost and feature extension has resulted in FPGA(s) becoming the preferred platform for evaluating and implementing DSP. The arithmetic circuits for addition and multiplication are the core of any DSP hardware as all the operations in DSP domain are a combination of these. In this work we have implemented the various forms of adder and multiplier circuits on FPGA, to have an analysis for finding out the most suitable arithmetic circuits for FPGA based DSP implementation. We present an analysis of our implementation results in respect to delay, power requirement and implementation costs of the different 8, 16, 32 and 64 bit circuits that can be realized for implementing the basic fixed-point arithmetic units in FPGA.
Keywords :
adders; digital signal processing chips; field programmable gate arrays; fixed point arithmetic; logic design; low-power electronics; multiplying circuits; DSP application; DSP functional block; FPGA; Virtex-5; Xilinx XC5VLX30; digital signal processing; field programmable gate array; fixed-point arithmetic unit; low power arithmetic circuit; multiplier circuit; power efficient adder; Adders; Delay; Digital signal processing; Educational institutions; Field programmable gate arrays; Integrated circuit modeling; Very large scale integration; Arithmetic circuits; DSP; FPGA; Xilinx Xpower; adder circuits; low power design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication and Industrial Application (ICCIA), 2011 International Conference on
Conference_Location :
Kolkata, West Bengal
Print_ISBN :
978-1-4577-1915-8
Type :
conf
DOI :
10.1109/ICCIndA.2011.6146691
Filename :
6146691
Link To Document :
بازگشت