A Low Power and High Performance SOI SRAM Circuit Design with Improved Cell Stability

Author

Joshi, R.V. ; Chan, Y. ; Plass, D. ; Charest, T. ; Freese, R. ; Sautter, R. ; Huott, W. ; Srinivasan, U. ; Rodko, D. ; Patel, P. ; Shephard, P. ; Werner, T.

Author_Institution

IBM T.J. Watson Res. Center, Yorktown Heights, NY

fYear

2006

fDate

2-5 Oct. 2006

Firstpage

4

Lastpage

7

Abstract

An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm partially depleted silicon on insulator (PD SOI) technology. The design features shorter bitlines (16 cells/bitline) along with a thin cell layout and programmable domino read operation. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability. In addition, the SRAM is supplied with multiple supplies: one to the cells, wordline drivers, and level shifters, and the other to the bitline and remaining logic to improve stability and lower power

Keywords

CMOS memory circuits; SRAM chips; low-power electronics; nanoelectronics; programmable circuits; silicon-on-insulator; 65 nm; CMOS static random access memory; SOI SRAM circuit; Si; cell accesses; improved cell stability; low power SRAM; partially depleted silicon on insulator; programmable domino read operation; thin cell layout; CMOS technology; Circuit stability; Circuit synthesis; Clocks; Decoding; Driver circuits; Random access memory; SRAM chips; Silicon on insulator technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

International SOI Conference, 2006 IEEE

Conference_Location

Niagara Falls, NY

ISSN

1078-621X

Print_ISBN

1-4244-0289-1

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2006.284405

Filename

4062853