A combinatorial approach to suppress leakage power in nanoscale SRAM cells

In deep sub-100nm technologies, the exponential increase of static leakage current pose serious design challenges as we try to build efficient low power systems with faster memory cores. Consequently, it is imperative to design systems that adopt leakage control techniques during both standby and active mode. In the recent past, the size of memory cores also has been increasing at a very rapid pace to cope with the demands of high computing processors. Such large memory cores will lead to significant leakage power dissipation, as most of the devices will be in a dormant or standby mode. This study addresses the static current dissipation problem in an SRAM memory core, by implementing a combinatorial approach to reduce leakage current. In this approach we have combined multiple-Vth devices, high-oxide thickness devices and dynamic Vth techniques to reduce both subthreshold and gate-oxide leakage current. There is a ~60% savings in the total static current dissipated as compared to a conventional SRAM cell