Analysis and reduction of ground bounce noise and leakage current during mode transition of stacking power gating logic circuits

Power gating is an effective method to reduce leakage current in logic circuits during sleep mode. However, conventional power gating technique for minimizing leakage current introduces ground bounce noise during sleep to active mode transition. In this paper, a high performance stacking power gating structure is introduced which minimizes the leakage power and provides a way to control the ground bounce noise in transition mode. Stacking power gating technique has been analyzed and the conditions for the important design goals such as (i) Minimum ground bounce noise and (ii) Minimum wakeup latency have been derived. The tradeoff between the ground bounce noise and wakeup latency has been explored for high performance power gating logic circuits. Further, to evaluate the efficacy of the proposed stacking power gating technique, simulation has been done using proposed technique and implemented on basic 2-input NAND gate circuit with BPTM 90 nm technology. The leakage current is reduced by 81.1% over the conventional power gating technique. Ground bounce noise has also been reduced to 76.28% as comparison to the conventional power gating technique.