Performance Enhancement for Ultra Thin Body MOSFETs Using Ultra Thin Spacer

As planar MOSFETs are scaled down, it is more and more difficult to achieve the scaled transistors with high performance. One of the key issues must be large source/drain (S/D) resistance as well as short channel effects (SCEs) (Ghani et al., 2001). These are in trade-off relation because shallow junction for reducing SCEs causes the increase of S/D resistance. One of the solutions to solve both problems may be elevated S/D technique. However, it seems to be another burden in consideration of growing the epitaxial layers on thin body (Widodo et al., 2005). Another solution is to reduce the spacer thickness (Yang et al., 2003). Through this approach, we can reduce the S/D resistance without any sacrifice of short channel effect (SCE) immunity. The requirements of spacer thickness and parasitic S/D resistance along technology node are shown in this paper. Recently, we proposed and successfully demonstrated partially insulated MOSFETs (PiFETs) as an alternative of ultra thin body (UTB) SOI devices (Kim et al., 2005). These are free from floating body, heat dissipation and high cost in comparison with conventional UTB SOI transistors. Despite of these merits, PiFETs like UTB SOI devices still suffer from large S/D resistance as their gate length are scaled down. In this paper, we evaluate characteristics of bulk MOSFETs with ultra thin spacer (UTS) and demonstrate the improved performance of 16 nm UTS PUC MOSFETs among PiFETs due to reduced S/D resistance