Title :
Transistor design issues in integrating analog functions with high performance digital CMOS
Author :
Chatterjee, A. ; Vasanth, K. ; Grider, D.T. ; Nandakumar, M. ; Pollack, G. ; Aggarwal, R. ; Rodder, M. ; Shichijo, H.
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Pocket or halo designs used in high performance digital CMOS design can degrade analog device performance. A new understanding of this phenomenon is presented using device simulation. The effect of pocket implant parameters on the trade-off between digital and analog performance is studied experimentally. Experimental data showing the beneficial effects of eliminating the pocket selectively from the drain end on analog performance is also shown.
Keywords :
CMOS integrated circuits; MOSFET; circuit simulation; doping profiles; integrated circuit design; integrated circuit measurement; ion implantation; mixed analogue-digital integrated circuits; analog device performance; analog function integration; analog performance; device simulation; digital CMOS; digital CMOS design; digital performance; halo designs; pocket designs; pocket implant parameters; selective drain end pocket elimination; transistor design issues; CMOS technology; Circuit simulation; Degradation; Design optimization; Doping profiles; Implants; Instruments; Integrated circuit interconnections; MOSFET circuits; Silicon;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799386
