New embedded DRAM technology using self-aligned salicide block (SSB) process for 0.18 /spl mu/m SOC (system on a chip)

Author

Kokubun, K. ; Takato, H. ; Sakurai, T. ; Koike, H. ; Nomachi, A. ; Ohtsuka, H. ; Harakawa, H. ; Sato, W. ; Tanaka, M. ; Naruse, H. ; Kamijo, H. ; Kumagai, J. ; Ishiuchi, H.

Author_Institution

ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1999

fDate

14-16 June 1999

Firstpage

155

Lastpage

156

Abstract

New embedded DRAM technology for 0.18 /spl mu/m SOC (system on a chip) using the self-aligned salicide block (SSB) process is proposed. This process technology provides full process compatibility with high performance logic and minimum number of process steps, resulting in low process cost and short TAT (turnaround time). We fabricated a DRAM array macro using this technology with Co salicide, dual work function gate and aluminum bitline processes, and confirmed excellent DRAM retention characteristics by using a negative wordline bias scheme.

Keywords

DRAM chips; embedded systems; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated logic circuits; microprocessor chips; work function; 0.18 micron; Al; Co salicide process; CoSi/sub 2/; DRAM array macro; DRAM retention characteristics; SOC; SSB process; aluminum bitline process; dual work function gate process; embedded DRAM technology; high performance logic process; negative wordline bias scheme; process compatibility; process cost; process steps; process technology; self-aligned salicide block process; system on a chip; turnaround time; Amplitude modulation; Capacitors; Cost function; Degradation; Dielectrics; Image storage; Logic arrays; Logic devices; Random access memory; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799390

Filename

799390