Title :
Low-temperature metal/ON/HSG-cylinder capacitor process for high density embedded DRAMs
Author :
Yamamoto, I. ; Honma, I. ; Yamamoto, T. ; Urabe, K. ; Inoue, K. ; Takaishi, Y. ; Yamada, Y. ; Tokunaga, K. ; Kubota, R. ; Hamada, M. ; Kato, Y.
Author_Institution :
ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan
Abstract :
A logic-process-compatible low-temperature hemispherical grain (HSG) cylinder capacitor process with maximum process temperature below 700/spl deg/C is developed. Depletion in HSG-grains and top-electrodes due to decreasing thermal budget is effectively suppressed by phosphorus doping with PH/sub 3/-annealing and the use of metal plate-electrodes. By combining with the HSG grain size optimization, the low-temperature process with highly reliable oxynitride (ON) dielectrics can be applied to high density embedded DRAM cells down to 0.13 /spl mu/m design rules.
Keywords :
DRAM chips; annealing; capacitors; circuit optimisation; dielectric thin films; doping profiles; embedded systems; grain size; integrated circuit design; integrated circuit manufacture; integrated circuit reliability; 0.13 micron; 700 C; HSG grain size optimization; HSG-grain depletion; PH/sub 3/; PH/sub 3/-annealing; SiON; design rules; high density embedded DRAM cells; high density embedded DRAMs; logic-process-compatible low-temperature HSG cylinder capacitor process; low-temperature hemispherical grain cylinder capacitor process; low-temperature metal/ON/HSG-cylinder capacitor process; low-temperature process; metal plate-electrodes; phosphorus doping; process temperature; reliable oxynitride dielectrics; thermal budget; top-electrode depletion; Capacitance; Capacitors; Degradation; Doping; Electrodes; Grain size; Logic devices; Random access memory; Temperature distribution; Ultra large scale integration;
Conference_Titel :
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-93-X
DOI :
10.1109/VLSIT.1999.799391
