DocumentCode
3252315
Title
Future perspective and scaling down roadmap for RF CMOS
Author
Morifuji, E. ; Momose, H.S. ; Ohguro, T. ; Yoshitomi, T. ; Kimijima, H. ; Matsuoka, F. ; Kinugawa, M. ; Katsumata, Y. ; Iwai, H.
Author_Institution
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
fYear
1999
fDate
14-16 June 1999
Firstpage
163
Lastpage
164
Abstract
The concept of future scaling-down for RF CMOS technology has been investigated in terms of f/sub T/, f/sub max/, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are key parameters, especially in sub-100 nm gate length generations.
Keywords
CMOS integrated circuits; circuit simulation; field effect MMIC; integrated circuit design; integrated circuit noise; integrated circuit testing; technological forecasting; 100 nm; RF CMOS; RF CMOS technology; RF noise; downscaling; finger length; gate length; gate width; linearity; matching characteristics; maximum frequency; simulation; threshold frequency; CMOS logic circuits; Circuit noise; Fingers; Laboratories; Linearity; Mice; Microelectronics; Noise figure; Radio frequency; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-93-X
Type
conf
DOI
10.1109/VLSIT.1999.799394
Filename
799394
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