Micro IDDQ test using Lorentz force MOSFET´s

Recently, the number of transistors in VLSIs has increased rapidly, which makes it difficult to find the locations of design errors and/or the locations of small circuit/process margins. The most common design errors are bridges and opens in interconnections. In order to detect these design errors and achieve low operational and standby currents, the IDDQ test is effective. In the conventional IDDQ test, however, the locations of these problems can not be identified, since only the currents of several power supply lines that are separated internally and have separate external pins can be checked. As each power supply line connects to so many transistors, it is impossible to pinpoint the error locations. It is possible to identify the location of errors if the current of thousands of internal power supply lines can be checked. In this paper, a current sensing device, the Lorentz force MOSFET (LMOS), is proposed to achieve this goal. The LMOS makes a noncontact and nondisturbing current measurement possible, which is different from the insertion of resistors in the power supply lines which degrades circuit speed in normal operation. It is also possible to check the quiescent current of thousands of macros on a chip, which we call a micro IDDQ test. While magnetic sensing devices have also been reported (Doyle and Lyden, 1994; Hone-Ming Yang et al., 1997), they are not suitable for micro IDDQ tests.