Title :
Wafer bonding for Planar Double Gate Technology
Author :
Dao, T. ; Seacrist, M. ; Ries, M. ; Kellerman, B.
Author_Institution :
Microwave & Mixed-Signals Technol. Lab., Austin, TX
Abstract :
In this paper, the authors report Freescale Semiconductor and MEMC collaboration to provide SOI wafers with bottom gate structures, SiON/polysilicon and high-K/metal gates, under the single crystalline silicon channel layer
Keywords :
field effect transistors; high-k dielectric thin films; silicon compounds; silicon-on-insulator; wafer bonding; Freescale Semiconductor; MEMC collaboration; SOI wafers; SiON; bottom gate structures; high-K/metal gates; planar double gate technology; single crystalline silicon channel layer; wafer bonding; Batteries; High K dielectric materials; High-K gate dielectrics; Manufacturing processes; Microwave technology; Plasma applications; Plasma immersion ion implantation; Silicon; Substrates; Wafer bonding;
Conference_Titel :
International SOI Conference, 2006 IEEE
Conference_Location :
Niagara Falls, NY
Print_ISBN :
1-4244-0289-1
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2006.284428
