DocumentCode
3252407
Title
Wafer bonding for Planar Double Gate Technology
Author
Dao, T. ; Seacrist, M. ; Ries, M. ; Kellerman, B.
Author_Institution
Microwave & Mixed-Signals Technol. Lab., Austin, TX
fYear
2006
fDate
2-5 Oct. 2006
Firstpage
51
Lastpage
52
Abstract
In this paper, the authors report Freescale Semiconductor and MEMC collaboration to provide SOI wafers with bottom gate structures, SiON/polysilicon and high-K/metal gates, under the single crystalline silicon channel layer
Keywords
field effect transistors; high-k dielectric thin films; silicon compounds; silicon-on-insulator; wafer bonding; Freescale Semiconductor; MEMC collaboration; SOI wafers; SiON; bottom gate structures; high-K/metal gates; planar double gate technology; single crystalline silicon channel layer; wafer bonding; Batteries; High K dielectric materials; High-K gate dielectrics; Manufacturing processes; Microwave technology; Plasma applications; Plasma immersion ion implantation; Silicon; Substrates; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
International SOI Conference, 2006 IEEE
Conference_Location
Niagara Falls, NY
ISSN
1078-621X
Print_ISBN
1-4244-0289-1
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2006.284428
Filename
4062876
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