A Fault-Tolerant Complex FIR Filter for SoC Communication Technologies

System-on-chip (SoC), the ability to put hundreds of millions of transistors on a chip "with as least fuss as possible", has allowed a natural evolution to the building of complete heterogeneous systems on a single monolithic silicon die. However, besides the many fabrication issues, many new design issues have also surfaced during this SoC evolution. In this paper we present preliminary fabrication results that address the SoC issues of inherent parallel computation, low redundancy, fault tolerance and current inrush reduction. Our target application is an adaptive equalization filter for the base station of an experimental 1.2 Gbps wireless LAN. The filter architecture is based on a quadratic modulus replication RNS, where the properties of the QMRRNS have been exploited to implement a low cost fault-tolerant architecture with independent computing channels.