Title :
Optimizing History Effects in 65nm PD-SOI CMOS
Author :
Liang, Q. ; Kawamura, T. ; Ketchen, M. ; Kawanaka, S. ; Pelella, Mario M. ; Robertson, D. ; Bhushan, M. ; McStay, K. ; Freeman, G. ; Miyamoto, At ; Leobandung, E. ; Huang, S.
Author_Institution :
IBM Syst. & Technol. Group, Sony Electron. Inc., Hopewell Junction, NY
Abstract :
History effects in 65-nm partially-depleted silicon-on-insulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit designs
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; silicon-on-insulator; 65 nm; PD-SOI CMOS; SOI circuit designs; Si; hardware data; history effects optimization; CMOS technology; Capacitance; Circuit synthesis; Degradation; Delay; History; Leakage current; Performance loss; Threshold voltage; Tunneling;
Conference_Titel :
International SOI Conference, 2006 IEEE
Conference_Location :
Niagara Falls, NY
Print_ISBN :
1-4244-0289-1
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2006.284450
