Title :
Impact of FD-SOI on Deep-Sub-100-nm CMOS LSIs -A View of Memory Designers-
Author :
Itoh, K. ; Yamaoka, M. ; Kawahara, T.
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo
Abstract :
A planar double-gate FD-SOI is compared with the bulk CMOS in terms of low-voltage operations. It turns out that due to the small VT variation the FD-SOI is suitable for deep-sub-1 V operations with improved voltage margin of RAM cells and sense amplifiers, and reduced speed variations of logic gates
Keywords :
CMOS integrated circuits; integrated circuit design; large scale integration; logic gates; low-power electronics; random-access storage; silicon-on-insulator; CMOS LSI; FD SOI; RAM cells; logic gates; low voltage operations; memory design; sense amplifiers; CMOS logic circuits; Conference proceedings; Degradation; Ice; Inorganic materials; Random access memory; Tin; Voltage;
Conference_Titel :
International SOI Conference, 2006 IEEE
Conference_Location :
Niagara Falls, NY
Print_ISBN :
1-4244-0289-1
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2006.284455
