DocumentCode :
325294
Title :
Fair queueing for input-buffered switches with back pressure
Author :
Li, Shizhao ; Chen, Jian-Guo ; Ansari, Nirwan
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fYear :
1998
fDate :
22-24 Jun 1998
Firstpage :
252
Lastpage :
259
Abstract :
The output-buffered switching architecture with its ability to offer high throughput, guaranteed delay and fairness, is not practical owing to its lack of scalability, i.e., the memory size, speed, and control logic have to be scaled up proportionally to the number of input links, thus becoming infeasible for large switches. The commercial and research trend is to adopt an architecture with input buffering which is scalable, but yields lower throughput and lacks the quality-of-service features such as delay bound and fairness. Although the problem of low throughput owing to head of line blocking in input-buffered switches can be resolved by adopting per-output-port queueing in each input port, the contention among input ports still limits the throughput. Existing schedulers designed for input-buffered switches attempt to improve throughput by imposing back pressure to the contending cells, and scheduling cells free of contention for transmission, at the expense of delay and fairness. In this paper, we have modeled and analyzed the back pressure with an independent Bernoulli traffic load, and we have shown that there is a high probability of back pressure occurring under loaded traffic. We have also derived the average queue length at the input buffer. To address the above issues in input-buffered switches, we proposed a new algorithm, referred to as min-max fair input queueing (MFIQ), which minimizes the additional delay caused by back pressure and at the same time provides fair service among competing sessions
Keywords :
asynchronous transfer mode; buffer storage; electronic switching systems; minimax techniques; queueing theory; scheduling; telecommunication traffic; ATM switches; Bernoulli traffic load; back pressure; delay bound; delay minimising; fair service; fairness; head of line blocking; input port; input-buffered switches; min-max fair input queueing; output-buffered switching architecture; per-output-port queueing; probability; quality-of-service features; queue length; scalability; scalable input buffering; scheduler design; scheduling cells; throughput limit; Delay; Logic; Proportional control; Quality of service; Scalability; Size control; Switches; Telecommunication traffic; Throughput; Traffic control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ATM, 1998. ICATM-98., 1998 1st IEEE International Conference on
Conference_Location :
Colmar
Print_ISBN :
0-7803-4982-2
Type :
conf
DOI :
10.1109/ICATM.1998.688185
Filename :
688185
Link To Document :
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