DocumentCode
3253034
Title
A 1 V 0.8mW multi-GHz CMOS differential tunable image reject notch filter
Author
Baki, Rola A. ; El-Gamal, Mourad N.
Author_Institution
RFIC Lab., McGill Univ., Montreal, Que., Canada
fYear
2005
fDate
7-10 Aug. 2005
Firstpage
802
Abstract
This paper presents a new implementation of a CMOS differential image reject filter at 8 GHz, combined with a folded-cascode 5.8 GHz low-noise amplifier, aiming at implementing fully integrated heterodyne receiver frontends. The filter consumes 0.8 mW from a 1 V supply, while providing 58 dB of image rejection in a standard CMOS 0.18 μm technology. Q-enhancement circuitry for on chip inductors are used to optimize the depth of image rejection.
Keywords
CMOS integrated circuits; Q-factor; image processing; low noise amplifiers; notch filters; 0.18 micron; 0.8 mW; 1 V; 5.8 GHz; 8 GHz; CMOS differential image reject filter; CMOS technology; Q-enhancement circuitry; folded-cascode low-noise amplifier; heterodyne receiver front-end; image rejection; notch filter; on-chip inductors; Capacitors; Computed tomography; Differential amplifiers; Filters; Impedance; Inductors; Radio frequency; Tunable circuits and devices; Voltage-controlled oscillators; Zinc;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. 48th Midwest Symposium on
Print_ISBN
0-7803-9197-7
Type
conf
DOI
10.1109/MWSCAS.2005.1594222
Filename
1594222
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