DocumentCode :
3253068
Title :
FPGA implementation of an image segmentation algorithm using logarithmic arithmetic
Author :
Bannister, Richard ; Gregg, David ; Wilson, Simon ; Nisbet, Andy
Author_Institution :
Dept. of Comput. Sci., Trinity Coll. Dublin
fYear :
2005
fDate :
7-10 Aug. 2005
Firstpage :
810
Abstract :
Image segmentation is a process used in computer vision to automatically divide up an image. We investigate the suitability of FPGAs and Log Arithmetic for image processing. We implemented a Bayesian pixel-based segmentation algorithm in hardware, and found that certain portions of the algorithm running on a mid-range FPGA could significantly outperform an implementation running on a high-end PC
Keywords :
computer vision; field programmable gate arrays; image segmentation; Bayesian pixel-based segmentation algorithm; FPGA; computer vision; image segmentation; logarithmic arithmetic; Arithmetic; Bayesian methods; Computer vision; Educational institutions; Field programmable gate arrays; Hardware; Image segmentation; Libraries; Pixel; Programmable logic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Conference_Location :
Covington, KY
Print_ISBN :
0-7803-9197-7
Type :
conf
DOI :
10.1109/MWSCAS.2005.1594224
Filename :
1594224
Link To Document :
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