DocumentCode :
3253245
Title :
Switched-opamp technique for 1-V 12-bit pipelined ADC
Author :
Nabavi, Mohammad Reza ; Lotfi, Reza
Author_Institution :
Dept. of ECE, Ferdowsi Univ., Mashhad, Iran
fYear :
2005
fDate :
7-10 Aug. 2005
Firstpage :
851
Abstract :
In this paper, a very low voltage low power high resolution pipelined ADC is presented. Several challenges in very low voltage high resolution ADC design are addressed and a low-power design methodology for switched-opamp (SO) converters is presented. This methodology determines the optimum values of all capacitors, including the compensation capacitors of the opamps and also the stage resolutions that will lead to minimum power consumption for a specified value of signal-to-noise ratio. For a 12-bit ADC, a novel 2.5-bit first stage is followed by eight 1.5-bit stages and a 2-bit back-end flash ADC. Design considerations and simulation results of the 12-bit 1-V 10MS/s pipelined SO ADC with low power consumption are also presented.
Keywords :
analogue-digital conversion; low-power electronics; network synthesis; operational amplifiers; switched networks; 1 V; high resolution; low power; low voltage; pipelined ADC; switched opamp; Capacitors; Clocks; Design methodology; Energy consumption; Feedback; Low voltage; Power dissipation; Signal resolution; Signal to noise ratio; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Print_ISBN :
0-7803-9197-7
Type :
conf
DOI :
10.1109/MWSCAS.2005.1594235
Filename :
1594235
Link To Document :
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