Title :
Area-efficient layout design of comparator using cascaded technique
Author :
Trikha, Manish ; Mehra, Rajesh
Author_Institution :
Dept. of Electron. & Commun, NITTTR, Chandigarh, India
Abstract :
In this paper a new design of cascaded comparator is described. Comparator is the basic building block of many arithmetic and logical units used in microprocessors and DSP. In the world of new emerging technology it has become essential to develop various new design concepts to reduce the power consumption and chip area. In this paper a semi-custom design of cascaded comparator has been presented and compared with the auto-generated layout on CMOS 90nm foundry technology. The proposed semi-custom design of cascaded comparator has showed an improvement of 35.65 % of total area as compared to auto-generated layout.
Keywords :
comparators (circuits); microprocessor chips; power aware computing; CMOS foundry technology; DSP; area-efficient layout design; arithmetic units; cascaded comparator; cascaded technique; chip area; logical units; microprocessors; power consumption; semicustom design; CMOS integrated circuits; CMOS technology; Complexity theory; Layout; Logic gates; Power dissipation; Very large scale integration; Area efficiency; CMOS technology; Cascaded Comparator; Very large scale integration;
Conference_Titel :
Computer Engineering and Applications (ICACEA), 2015 International Conference on Advances in
Conference_Location :
Ghaziabad
DOI :
10.1109/ICACEA.2015.7164765
