Applying SOI Technology on Carbon Nanotube Transistors

Author

Zhang, Min ; Chan, Philip C.H. ; Chai, Yang ; Tang, Zikang

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol.

fYear

2006

fDate

2-5 Oct. 2006

Firstpage

147

Lastpage

148

Abstract

By combining the advantages of the SOI technology and in situ carbon nanotube growth technology, we have realized the local silicon-gate CNFETs with individual device operation, low parasitic capacitance, high yield fabrication, and better compatibility to the CMOS process. The CNFETs show excellent electrical performance. Further improvement can be obtained on the CNFET performance by scaling and by changing electrode. The configuration proposes a feasible solution for the integration of carbon nanotube to CMOS circuits

Keywords

CMOS integrated circuits; carbon nanotubes; elemental semiconductors; field effect transistors; silicon; silicon-on-insulator; CMOS circuits; CMOS process; SOI technology; Si; carbon nanotube transistors; high yield fabrication; in situ carbon nanotube growth technology; parasitic capacitance; silicon-gate CNFET; CMOS technology; Carbon nanotubes; Contact resistance; Crystallization; Dielectrics; Fabrication; MOSFET circuits; Semiconductor films; Silicon on insulator technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

International SOI Conference, 2006 IEEE

Conference_Location

Niagara Falls, NY

ISSN

1078-621X

Print_ISBN

1-4244-0289-1

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2006.284479

Filename

4062927