Title :
Reducing RMS noise in CMOS dynamic reconfigurable latched comparator in 50 nm
Author :
Kumar, Murari ; Singhal, Manish
Author_Institution :
Dept. of Electron. (Specialization in VLSI), Poornima Coll. of Eng., Jaipur, India
Abstract :
This paper presents a new dynamic reconfigurable CMOS latched comparator that demonstrates low RMS noise, low offset and high gain. In this dynamic comparator circuit we make an independent inputs transistor and its input inverter circuit PMOS connected to clk1 with tail transistor. The proposed comparator circuit shows better RMS noise response i.e. 704.38μV as compare to previous comparator circuit i.e. 1.1208mV and better output driving capacity as compare to conventional comparator circuit. The proposed comparator is simulated and implemented in LT SPICE 50nm technology.
Keywords :
CMOS digital integrated circuits; SPICE; comparators (circuits); flip-flops; logic gates; CMOS dynamic reconfigurable latched comparator; RMS noise reduction; SPICE technology; complementary metal oxide semiconductor; driving capacity; dynamic comparator circuit; independent input transistor; inverter circuit PMOS; size 50 nm; CMOS integrated circuits; Clocks; Inverters; Latches; Noise; SPICE; Transistors; CMOS Comparator; LT SPICE; RMS Noise; amplifier;
Conference_Titel :
Computer Engineering and Applications (ICACEA), 2015 International Conference on Advances in
Conference_Location :
Ghaziabad
DOI :
10.1109/ICACEA.2015.7164766