A flipped voltage follower based analog multiplier in 90nm CMOS process

Author

Satapathy, Amarjyoti ; Maity, Subir Kumar ; Mandal, Sushanta K.

Author_Institution

Sch. of Electron. Eng., KIIT Univ., Bhubaneswar, India

fYear

2015

fDate

19-20 March 2015

Firstpage

628

Lastpage

631

Abstract

In this paper, a five transistor voltage adder, consisting of a flipped voltage follower devised to work in low voltage rail, has been used as the main building block for designing an analog multiplier. Four of such cells have been used for biasing and signaling. This Multiplier has been designed using GPDK 90nm CMOS technology and simulated in Cadence Spectre environment. The supply voltage has been taken as 1-Volt. In worst case the multiplier consumes 178 μW power and perfectly working up to 454.56 MHz with less than 1.5% harmonic distortion components.

Keywords

CMOS analogue integrated circuits; analogue multipliers; low-power electronics; operational amplifiers; CMOS process; Cadence Spectre; flipped voltage follower based analog multiplier; power 178 muW; size 90 nm; voltage 1 V; voltage adder; CMOS integrated circuits; Computers; Layout; Low voltage; Threshold voltage; Transistors; Very large scale integration; Amplitude Modulation; Analog Multiplier; Flipped Voltage Follower; Low voltage design technique; Source Follower;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Applications (ICACEA), 2015 International Conference on Advances in

Conference_Location

Ghaziabad

Type

conf

DOI

10.1109/ICACEA.2015.7164767

Filename

7164767