A fast heuristic for leakage-aware synthesis

With decreasing device sizes, and especially in the nanometer realm, the leakage power is growing and is in excess of 40% of the total power consumption. Therefore, methods are needed that reduce the leakage power. This work considers power minimization during high-level synthesis through a fast heuristic scheduling algorithm to reduce the leakage power. The proposed synthesis system constructs a library of functional units with subunits operating either at a high threshold voltage or a low threshold voltage. Consequently, the library is populated with several design choices with respect to the leakage power dissipation and speed offered. The input to the system is a behavioral description of the circuit to be synthesized. The proposed scheduling algorithm tames the complexity of the optimal scheduling (a well known NP-Complete problem) through a low-complexity heuristic scheduling. The details of the algorithm, complexity analysis, illustration on simple test cases, as well as the results obtained on the standard benchmarks are presented. The results (i.e., synthesized, time-scheduled structure) show significant reduction in the leakage power without sacrificing the original speed