Automatic biasing point extraction and design plan generation for analog IPs

In this paper, an algorithm for automatic extraction of DC biasing point towards generation of design plans is presented. Initially, the circuit is described as a hierarchy of modules and devices inside our dedicated framework CAIRO+. Electrical information is propagated from higher level modules, to lower level ones, till reaching the device level. During navigation through the hierarchy, a dependency subgraph is generated for each device and module. Each subgraph expresses electrical dependencies by choosing among a set of predefined sizing operators. To obtain a final directed acyclic graph, existing graph directed cycles are detected and removed. The resulting graph represents the complete sizing procedure for the analog IP. The calculated biasing point is compared against operating point simulation. The algorithm is successfully applied to two analog IPs: single-ended two-stages output transconductance amplifier and differential cascode current-mode integrator