A 50 nm vertical Si0.70Ge0.30/Si0.85 Ge0.15 pMOSFET with an oxide/nitride gate dielectric

Vertical Reduced Pressure Chemical Vapour Deposition (RP-CVD) grown heterojunction pMOS transistors with a Si_0.70Ge_0.30/Si_0.85Ge_0.15 source stack have been fabricated with channel lengths down to 50 nm on a strain relaxed Si_0.85Ge_0.15 buffer layer. This paper reports on the viability of this source stack to suppress short channel effects in this channel length region. This is done by comparing the electrical characteristics of vertical Si_0.85Ge_0.15 homojunction transistors, and vertical Si_0.70Ge_0.30/Si_0.85Ge_0.15 heterojunction transistors, with channel lengths of 90 nm and 50 nm