Title :
What are the building blocks of nanoprocessor architecture?
Author :
Teller, Justin ; Ewing, Robert ; Ozguner, Fusun
Author_Institution :
Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH
Abstract :
The design goal of the nanoprocessor architecture is to build a high performance but flexible parallel machine. High performance is achieved through explicit support for parallelism in both hardware and software. Flexibility is gained by defining a nanoprocessor as a specialized processing element. Nanoprocessor architecture consists of a large number of tightly coupled, heterogeneous nanoprocessors. Flexibility in a nanoprocessor´s function allows for the integration of new computing technologies into an existing design framework. New computing structures may arise from nanotechnology, biology, or other sciences. Even discounting the addition of new technologies, there is a need to update processing architectures to execute with more parallelism. An efficient parallel processing architecture can allow higher performance for next generation architectures. This paper introduces the building blocks for the nanoprocessor architecture and discusses some design trade-offs for the nanoprocessor itself, communication among nanoprocessors, memory organization, and the nanoprocessor architecture programming model
Keywords :
microprocessor chips; nanoelectronics; parallel architectures; parallel machines; parallel programming; flexible parallel machine; heterogeneous nanoprocessors; memory organization; nanoprocessor architecture; parallel processing architecture; Biology computing; Computational efficiency; Computer architecture; Hardware; Logic testing; Nanobioscience; Nanotechnology; Parallel processing; Pipeline processing; Software performance;
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Conference_Location :
Covington, KY
Print_ISBN :
0-7803-9197-7
DOI :
10.1109/MWSCAS.2005.1594254