Folded cascode CMOS mixer design and optimization in 70 nm technology

A 2.4 GHz CMOS RF mixer is designed using 70 nm technology in order to maximize potential efficiency and minimize power consumption. Running the circuit at low voltages brings in a concern for headroom, as it becomes more difficult to correctly bias stacks of transistors like those found in a standard Gilbert cell. In order to reliably run the circuit at 0.7 V, the Gilbert cell design is revised using the established concept of folded cascode. The revisions also serve to improve secondary features of the mixer such as linearity and input transistor transconductance. The simulated circuit exhibits a 1.4dB conversion loss, -11.5 dBm LO power, -0.5 dBm at the IPD and 0.7 mW consumed in the mixer itself.