Sharing FPGA SRAM tables among NPN equivalent LUTs

The analysis results of several LUT-level benchmarks indicate that a large percentage of the LUTs in a LUT-level circuit are NPN-equivalent. In this paper, we design a new logic block that allows sharing of SRAM tables and modify a packing algorithm to efficiently map equivalent functions into the same SRAM tables. By allowing only a certain percentage of the CLBs to share their SRAM tables, we could obtain similar routing results as with the original CLBs. When using NPN equivalence, one out of eight CLBs can allow their SRAM tables to be shared by equivalent LUTs without increasing channel width or FPGA dimensions