Title :
Early-late gate receiving for Bluetooth packet
Author :
Peng, Chia-Sheng ; Chang, Ming-Hung ; Wen, Kuei-Ann
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of an Analog-to-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis
Keywords :
application specific integrated circuits; digital radio; field programmable gate arrays; frequency hop communication; mobile radio; packet radio networks; radio receivers; spread spectrum communication; synchronisation; transceivers; ASIC implementation; Bluetooth V1.0 baseband specifications; Bluetooth V1.0 radio specifications; Bluetooth packet; FPGA emulation; early-late gate receiving; field programmable gate arrays; performance analysis; timing recovery algorithm; Baseband; Bluetooth; Circuits; Clocks; Communication cables; Correlators; Field programmable gate arrays; Frequency conversion; Frequency synthesizers; Timing;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-6412-0
DOI :
10.1109/VTSA.2001.934482
