Application-specific PLD targeting super semi-systolic designs

Author

Lee, Jae-Jin ; Song, Gi-Yong

Author_Institution

Dept. of Comput. Eng., Chungbuk Nat. Univ., Cheongju

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

968

Abstract

This paper proposes a new PLD architecture targeting a super semi-systolic array - a derivative from a super-systolic array - for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super semi-systolic array is ideal for a newly proposed PLD architecture in terms of area-efficiency, P&R and clock speed

Keywords

application specific integrated circuits; digital arithmetic; logic design; programmable logic devices; systolic arrays; ASIC; PLD architecture; application-specific arithmetic operations; programmable logic devices; super semi-systolic array; Clocks; Computer architecture; Concurrent computing; Digital arithmetic; Field programmable gate arrays; Finite impulse response filter; Latches; Pipelines; Programmable logic devices; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594264

Filename

1594264

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3253796