• DocumentCode
    3253803
  • Title

    Architectures for network processing

  • Author

    Williams, Joseph

  • Author_Institution
    Lucent Technol., Bell Labs., Holmdel, NJ, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    61
  • Lastpage
    64
  • Abstract
    Packet processing is the heart of most networking equipment. The network processor (NP) promises the ability to perform packet processing with the flexibility of a microprocessor but with the performance of a dedicated ASIC. In this paper, we survey common architectural features of most commercially available NPs. The NP is a programmable processor optimized to perform packet processing at wire rates in networking equipment. It is a classic tradeoff in the continuum of programmable processors verses dedicated hardware
  • Keywords
    application specific integrated circuits; computer architecture; network computers; NPs; common architectural feature; dedicated ASIC; network processing; packet processing; programmable processor; wire rates; Access protocols; Application specific integrated circuits; Bandwidth; Fabrics; Hardware; Microprocessors; Packet switching; Physical layer; Switches; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    1524-766X
  • Print_ISBN
    0-7803-6412-0
  • Type

    conf

  • DOI
    10.1109/VTSA.2001.934483
  • Filename
    934483
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3253803