Evaluating generalized semi Markov process model of SoC bus architectures using HCFG

This paper presents an efficient approach based on Hierarchical Concurrent Flow Graph (HCFG) for performance evaluation of single shared bus architecture and hierarchical bus bridge architecture. The formulation is based on generalized semi Markov process model of these architectures. In particular, we focus on building model for a single shared bus architecture and extend the approach to model architecture consisting of hierarchical buses connected through bus bridge. Our modeling approach provides early estimation of performance parameters viz. memory bandwidth, processor utilization, average queue length and average waiting time. We validate the proposed modeling and evaluation approach by comparing the results of evaluation against those that are obtained by SystemC simulation of the same communication architectures under consideration. The HCFG approach is not only time efficient but also provides much detailed evaluation of stochastic properties of performance parameters as compared to SystemC simulation. To illustrate the efficacy of the approach, we compare the results with the results available in the literature for some more examples.