A novel programmable frequency divider based on analog counter

Author

Vijayaraghavan, Rajagopal ; Islam, Syed K. ; Blalock, B.J. ; Srinivasan, Venkatesh

Author_Institution

Dept. of Electr. & Comput. Eng., Tennessee Univ., Knoxville, TN

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

996

Abstract

An analog programmable frequency divider (APFD) that is based on the concept of an analog counter is described. The divide ratio is set using the analog counter and a toggle flip-flop. A prototype programmable divider has been implemented in a 0.5mum standard digital CMOS process with divide ratios ranging from 16-30 in steps of 2 for a maximum input frequency of 10MHz. The divide ratio exhibits a weak logarithmic dependence on process, voltage and temperature (PVT) variations that can be addressed using resistor trimming. Simulation results have been provided that demonstrate both the functionality and feasibility of the proposed divider

Keywords

CMOS integrated circuits; flip-flops; frequency dividers; 0.5 micron; 10 MHz; APFD; analog counter; analog programmable frequency divider; digital CMOS process; resistor trimming; toggle flip-flop; weak logarithmic dependence; Capacitors; Circuit noise; Counting circuits; Flip-flops; Frequency conversion; Frequency synthesizers; Phase locked loops; Resistors; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594271

Filename

1594271