A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 Standard and its Efficient Implementation on a DSP Processor

This paper presents a real time programmable irregular low density parity check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on SC140 Processor and different optimization techniques are applied to enhance the throughput. With SC140, a reduction of 2.6 times in the number of effective MAC operations has been achieved, with further reduction in cycle counts possible. A pipelined architecture is also presented for possible ASIC or FPGA implementation.