A new rail-to-rail readout circuit of CMOS image sensor for low power applications

Author

Chow, Hwang-Cherng ; Hsiao, J.-B.

Author_Institution

Dept. & Graduate Inst. of Electron. Eng., Chang Gung Univ., Tao-Yuan

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1019

Abstract

In order to enhance the performance of CMOS image sensor under lower supply voltage, a new rail-to-rail pixel readout architecture is proposed in this paper. Due to the new readout circuit, the enough input voltage swing under low supply voltage is achieved and guaranteed for correct successive signal processing. As a consequence, the ability of working under lower voltage using the same process is greatly improved. The layout size of each pixel is 17mumtimes11.55mum. The design of a 64times64 bits CMOS image sensor circuit has been completed. The proposed CMOS image sensor can extend its operating voltage from 3.3V even down to 1.8V for a 0.35mum process. The total power dissipation is 0.528mW at 3.3V supply and down to 0.102mW at 1.8V

Keywords

CMOS image sensors; integrated circuit design; low-power electronics; readout electronics; 0.35 micron; 0.528 mW; 3.3 V; CMOS image sensor circuit; low power applications; rail-to-rail readout circuit; readout architecture; signal processing; CMOS image sensors; Charge coupled devices; Circuits; Digital cameras; Dynamic range; Low voltage; Pixel; Sensor arrays; Signal processing; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594277

Filename

1594277