Title :
Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication
Author_Institution :
Intel Corp., Chandler, AZ
Abstract :
A low power, small area receiver equalizer circuit based on novel threshold multiplexing (TMX) technique is presented. Simulation results based on the proposed sampler circuit and a 3-level 2-tap TMX equalizer circuit implementation show achievable 20~30 ps eye margin improvement for a 5 Gb/s high-speed serial I/O application. This circuit demonstrates a very low PVT sensitivity and extremely wideband operation, which is fully digital and highly scalable and therefore very suitable for SOC applications.
Keywords :
data communication; equalisers; high-speed techniques; multiplexing; receivers; system-on-chip; PVT sensitivity; SOC; TMX equalizer circuit; high-speed serial data communication; receiver equalization circuit; sampler circuit; threshold multiplexing technique; Circuit simulation; Clocks; Data communication; Dielectric losses; Digital signal processing; Equalizers; Latches; Sampling methods; Very large scale integration; Wideband;
Conference_Titel :
SOC Conference, 2006 IEEE International
Conference_Location :
Taipei
Print_ISBN :
0-7803-9781-9
Electronic_ISBN :
0-7803-9782-7
DOI :
10.1109/SOCC.2006.283840
