Fast, automated thermal simulation of three-dimensional integrated circuits

Three-dimensional (3D) stacked integrated circuits (ICs) can significantly improve circuit performance and offer the promise of integrating various technologies (memory, logic, RF, mixed-signal, optoelectronics) within a single block. Lack of 3D design tools and heat dissipation from vertically stacked multiple layers are the crucial problems in their development. To address these issues, CFD Research Corporation (CFDRC) is developing methodologies and tools to analyze and assess coupled electrical and thermal performance of 3D ICs, including calculation of realistic full-chip thermal distributions and determining from them signal delay/distortion. Due to the stacking technology, extensive localized heating can occur. Analysis to minimize these hot spots using thermal vias is demonstrated. Our Python-script based framework allows to drive and control all the aspects of the 3D model building (directly from layouts), thermal simulations, and results extraction/post-processing. Hence, it is a good basis for coupling with Electronic Design Automation (EDA) systems. We present results of automated, fast, but detailed thermal simulations of 3D stacked integrated circuits. In addition, procedures for automatic extraction of reduced and compact thermal-resistance-based 3D models have been implemented. These techniques greatly reduce required computational time, and allow for very fast parametric modeling analysis of 3D IC design configurations and temperature extraction. From these thermal resistance models, equivalent SPICE netlists may be generated and used for independent or coupled thermal analysis.