DocumentCode :
3254217
Title :
Congestion-driven floorplanning by adaptive modular shaping
Author :
Huang, Hsin-Hsiung ; Chang, Chung-Chiao ; Lin, Chih-Yuan ; Hsieh, Tsai-Ming ; Lee, Chih-Hung
Author_Institution :
Inst. of Electron. Eng., Chung Yuan Christian Univ., Chung-Li
fYear :
2005
fDate :
7-10 Aug. 2005
Firstpage :
1067
Abstract :
In this paper, we implement a two-stage process to simultaneously minimize wire congestion and total wire-length at floorplanning stage. We first use a simulated-annealing approach with sequential-pair representation to find a floorplan with minimal wire congestion, total wire-length and area. Each of the two selected adjacent soft modules in congested region is then divided into a set of connected sub-rectangles to increase the common boundary between the adjacent modules. The longer common boundary actually reduces total wire-length between the pins of two modules and minimizes the wire congestion. A nonlinear programming method is used for modular shaping mentioned above to further minimize the wire congestion without the penalty of area. Compared to the traditional method without consideration of the modular shaping, we show experimentally that our algorithm achieves an average reduction rate of 22% and 1.54% in wire congestion and total wire-length, respectively
Keywords :
VLSI; circuit optimisation; integrated circuit layout; simulated annealing; adaptive modular shaping; congestion-driven floorplanning; minimal wire congestion; nonlinear programming; sequential-pair representation; simulated annealing; total wire-length; Grid computing; Lagrangian functions; Pins; Routing; Shape; Simulated annealing; Timing; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Conference_Location :
Covington, KY
Print_ISBN :
0-7803-9197-7
Type :
conf
DOI :
10.1109/MWSCAS.2005.1594289
Filename :
1594289
Link To Document :
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