A new interconnect-aware floorplan representation and its application to floorplanning targeting buffer planning

In this paper, we propose a new interconnect-aware floorplan representation named Segment List (SL), from which floorplans can be obtained in linear time. SL includes two sequences (S, L). The first sequence is an n - 1 binary sequence representing vertical or horizontal segments. The second one records the number of segments touching each segment from left(vertical segment)/below(horizontal segment). Segment List is independent of blocks name and it represents a dissection of the chip. We give a sufficient and necessary condition to ensure a feasible Segment List and a packing algorithm is also devised. Given a segment list, the floorplan can be changed by changing the assignments of blocks to rooms. The simulated annealing algorithm is adopted to search approximate optimal floorplans. Segment List defines well white space blocks and channels between blocks, which favors buffer planning. Therefore, a buffer planning algorithm based on Segment List is devised. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithms