DocumentCode
3254260
Title
A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOS
Author
Hansson, Martin ; Alvandpour, Atila
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Linkoping
fYear
2006
fDate
24-27 Sept. 2006
Firstpage
83
Lastpage
84
Abstract
This paper presents analysis and measurement of a leakage current compensation technique aimed to preserve traditional operation of dynamic flip-flops in nano-scale CMOS. Over 7.4X larger leakage tolerance was observed for a dynamic transmission-gate flip-flop utilizing the proposed technique. Furthermore, a conditional static keeper ensures robust operation at low-frequency/standby..
Keywords
CMOS logic circuits; compensation; flip-flops; leakage currents; nanoelectronics; dynamic flip-flops; dynamic latches; dynamic transmission-gate flip-flop; leakage compensation technique; leakage tolerance; nanoscale CMOS; CMOS technology; Circuit testing; Clocks; Current measurement; Flip-flops; Frequency; Latches; Leakage current; Subthreshold current; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2006 IEEE International
Conference_Location
Taipei
Print_ISBN
0-7803-9781-9
Electronic_ISBN
0-7803-9782-7
Type
conf
DOI
10.1109/SOCC.2006.283850
Filename
4063019
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