Algorithmic complexity, motion estimation and a VLSI architecture for MPEG-4 core profile video codecs

Author

Stechele, Walter

Author_Institution

Tech. Univ. Munchen, Germany

fYear

2001

fDate

2001

Firstpage

172

Lastpage

175

Abstract

A VLSI architecture with flexible, application-specific coprocessors for object based video encoding/decoding is presented. This architecture combines high performance of dedicated ASIC architectures with the flexibility of programmable processors. Dataflow and memory access were optimized based on extensive studies of statistical complexity variations. The architecture consists of a standard embedded core, as well as coprocessor modules for macroblock algorithms, motion estimation and bitstream processing. Results on silicon area and clock rate, required for realtime processing of MPEG-4 core profile video, are presented, as well as a comparison with software implementations on a standard RISC architecture

Keywords

VLSI; application specific integrated circuits; coprocessors; motion estimation; video codecs; MPEG-4 core profile video; VLSI architecture; algorithmic complexity; application-specific coprocessors; bitstream processing; clock rate; dataflow; macroblock algorithms; memory access; motion estimation; object based video encoding/decoding; statistical complexity variations; video codecs; Application specific integrated circuits; Clocks; Computer architecture; Coprocessors; Decoding; Encoding; MPEG 4 Standard; Motion estimation; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

0-7803-6412-0

Type

conf

DOI

10.1109/VTSA.2001.934512

Filename

934512