LUT error modeling based on implicit cube-distance errors

Author

Lee, Lucas W B ; Radecka, Katarzyna

Author_Institution

Dept. of Electr. Eng. & Comput. Eng., Concordia Univ., Montreal, Que.

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1135

Abstract

A new way of modeling FPGA functional faults by implicit cube-distance errors is proposed. The implicit fault model allows significant reduction in fault list size, which is of a particular importance in the case of mistakes in functions implemented by LUTs. Experiments are performed in a modified version of SIS where the quality of the model is tested by software emulation. Finally, methods of fault redundancy identification are also discussed

Keywords

field programmable gate arrays; logic design; table lookup; FPGA functional fault modeling; LUT error modeling; SIS tool; fault list size; fault redundancy identification; implicit cube-distance errors; software emulation; Aerospace electronics; Automatic test pattern generation; Circuit faults; Circuit testing; Computer errors; Fault diagnosis; Field programmable gate arrays; Manufacturing; Redundancy; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594306

Filename

1594306

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3254471