High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling

Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct coupling of data storage nodes to the bit lines during a read operation. Lowering of supply and threshold voltages leads to a significant degradation in SRAM cell stability with the scaling of CMOS technology. The SRAM cell stability is further degraded due to the process parameter variations in deeply scaled CMOS technologies. In addition to the data stability issues, the increasing leakage energy consumption of on-chip caches is another growing concern. In this paper, a new nine transistor (9T) SRAM cell with enhanced read stability and reduced leakage power consumption is proposed.