DocumentCode
3254605
Title
A Trace-Driven Validation Methodology for Multi-Processor SOCS
Author
Bhadra, Jayanta ; Trofimova, Ekaterina ; Giordano, Leonard J. ; Abadir, Magdy S.
Author_Institution
Freescale Semicond. Inc, Austin, TX
fYear
2006
fDate
24-27 Sept. 2006
Firstpage
145
Lastpage
148
Abstract
Multi-processor systems-on-chip pose a great challenge to validation due to their size and complexity. We approach the problem of MP SoC validation through a tool that uses a reusable scheme to effectively leverage a simulation-based abstraction scheme. Our tool checks an abstract representation of the system across traces obtained by simulating a system level implementation and analyzes the results for correctness. We have effectively used the tool on various live MP SoC design projects.
Keywords
circuit simulation; integrated circuit design; multiprocessing systems; system-on-chip; SoC design; abstract representation; design validation; multiprocessor SoC; multiprocessor systems-on-chip; simulation-based abstraction scheme; system level implementation; trace-driven validation methodology; Analytical models; Character generation; Computer bugs; Manufacturing processes; Memory management; Predictive models; Product design; Semiconductor device manufacture; Time to market; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2006 IEEE International
Conference_Location
Taipei
Print_ISBN
0-7803-9781-9
Electronic_ISBN
0-7803-9782-7
Type
conf
DOI
10.1109/SOCC.2006.283869
Filename
4063038
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