Layout issues in bus encoding schemes

With the scaling down of device and interconnect dimensions in very deep submicron technology, the increased wire aspect ratio and the reduced spacing between the individual wires within a bus results in increased cross-coupling capacitances. This increases crosstalk noise and power dissipation particularly in wide data buses. A number of schemes have been proposed that reduce correlated and self-switching among bus wires using additional control signals. We study the impact of layout related issues on some of the bus encoding schemes.