DocumentCode :
3254760
Title :
Analysis and architecture for memory efficient JBIG2 arithmetic encoder
Author :
Chen, Chun-Chia ; Chang, Yu-Wei ; Fang, Hung-Chi ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2005
fDate :
7-10 Aug. 2005
Firstpage :
1191
Abstract :
JBIG2 is the latest international standard for bilevel image compression. It partitions a bilevel image into three types of region - text, halftone, and generic region. This paper addresses the problem of large memory requirements for the contexts. The arithmetic encoders of text region in JBIG2 require a large memory for the contexts. In this work, we proposed several algorithms to reduce the memory requirements. A large portion of total memory requirements are reduced by the proposed algorithms. Moreover, the proposed algorithms are implemented as memory efficient hardware architecture, the unified arithmetic encoder. The experimental results show that the proposed algorithms are efficient. The proposed algorithms can reduce the memory requirements for the contexts by 98.7%. Moreover, the drop of coding gain due to memory reduction for the contexts is only 4.83% in average.
Keywords :
arithmetic codes; data compression; digital arithmetic; image coding; JBIG2 arithmetic encoder; bilevel image compression; coding gain; memory efficient hardware; memory reduction; unified arithmetic encoder; Arithmetic; Data mining; Design engineering; Dictionaries; Digital signal processing; Hardware; Image coding; Image segmentation; Memory architecture; Partitioning algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Print_ISBN :
0-7803-9197-7
Type :
conf
DOI :
10.1109/MWSCAS.2005.1594320
Filename :
1594320
Link To Document :
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