VLSI architecture of the soft-output sphere decoder for MIMO systems

Author

Guo, Zhan ; Nilsson, Peter

Author_Institution

Dept. of Electrosci., Lund Univ., Sweden

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1195

Abstract

Sphere decoders can approach the performance of maximum-likelihood (ML) decoders for MIMO systems with lower complexity. In this paper, VLSI architecture of the modified K-best Schnorr-Euchner (MKSE) sphere decoder is proposed for soft-output MIMO decoding. The MKSE decoder can achieve near-ML performance with higher decoding throughput and lower computational complexity. The proposed VLSI architecture is implemented for a 4 × 4 16-QAM MIMO system in a 0.13-μm CMOS technology. The implemented soft-output MKSE chip can achieve a decoding throughput of more than 100 Mb/s with a 0.56 mm² core area and 97 K gates.

Keywords

MIMO systems; VLSI; maximum likelihood decoding; quadrature amplitude modulation; 0.13 micron; 16-QAM MIMO system; CMOS technology; MKSE decoder; VLSI architecture; computational complexity; decoding throughput; maximum-likelihood decoders; modified K-best Schnorr-Euchner decoder; near-ML performance; soft-output sphere decoder; CMOS technology; Computational complexity; Computer architecture; Detectors; Iterative decoding; MIMO; Maximum likelihood decoding; Maximum likelihood detection; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594321

Filename

1594321