Title :
Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder
Author :
Tsai, Chuan-Yung ; Chen, Tung-Chien ; Chen, To-Wei ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
Design of H.264/AVC motion compensation (MC) is very challenging through the high memory bandwidth and low hardware utilization caused by the new functionalities of variable block size and 6-tap interpolation filter. In this paper, the vertically integrated double Z (VIDZ) schedule, and interpolation window reuse (IWR) and interpolation window classification (IWC) bandwidth reduction schemes are proposed to keep the MC highly utilized and save 60-80% memory bandwidth. The hardware of proposed MC is implemented at 120MHz with 47K logic gates and can support 2048 times 1024 30fps H.264/AVC HDTV decoder with less than 200MB/s memory bandwidth
Keywords :
filters; high definition television; interpolation; logic design; motion compensation; video codecs; 120 MHz; AVC HDTV decoder; H.264 decoder; interpolation filter; interpolation window classification; interpolation window reuse; logic gates; memory bandwidth reduction; motion compensation; vertically integrated double Z schedule; Automatic voltage control; Bandwidth; Decoding; Design optimization; Filters; HDTV; Hardware; Interpolation; Logic gates; Motion compensation;
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Conference_Location :
Covington, KY
Print_ISBN :
0-7803-9197-7
DOI :
10.1109/MWSCAS.2005.1594322
