An efficient VLSI architecture for JPEG2000 encoder

Author

Jung, Gab Cheon ; Park, Seong Mo ; Kim, Jung Hyoun

Author_Institution

Dept. of Electron. Eng., Chonnam Nat. Univ., Kwang-ju

fYear

2005

fDate

7-10 Aug. 2005

Firstpage

1203

Abstract

This paper presents an efficient VLSI architecture of JPEG2000 encoder that has high performance with low hardware complexity. The proposed architecture performs RPA (recursive pyramid algorithm) based 2D lifting DWT operations with the reduction of processing elements and bit-plane parallel EBCOT (embedded block coded with optimized truncation) operations using one bit-plane coder and binary arithmetic coder per two bit-planes. Together with multi-level processing of DWT, it conducts multi-level EBCOT operations as soon as M lines of each wavelet subband are available, where M is column size of code block. As a result, it can have fast computation time and reduce memory requirement

Keywords

VLSI; arithmetic codes; digital signal processing chips; discrete wavelet transforms; image coding; 2D lifting DWT operations; JPEG2000 encoder; VLSI architecture; binary arithmetic coder; embedded block coding; hardware complexity; memory requirement reduction; parallel EBCOT; recursive pyramid algorithm; truncation optimization; Arithmetic; Computer architecture; Discrete wavelet transforms; Filters; Hardware; Image coding; Image storage; Tiles; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. 48th Midwest Symposium on

Conference_Location

Covington, KY

Print_ISBN

0-7803-9197-7

Type

conf

DOI

10.1109/MWSCAS.2005.1594323

Filename

1594323