An efficient VLSI architecture for JPEG2000 encoder

This paper presents an efficient VLSI architecture of JPEG2000 encoder that has high performance with low hardware complexity. The proposed architecture performs RPA (recursive pyramid algorithm) based 2D lifting DWT operations with the reduction of processing elements and bit-plane parallel EBCOT (embedded block coded with optimized truncation) operations using one bit-plane coder and binary arithmetic coder per two bit-planes. Together with multi-level processing of DWT, it conducts multi-level EBCOT operations as soon as M lines of each wavelet subband are available, where M is column size of code block. As a result, it can have fast computation time and reduce memory requirement