Potential performance of parallel conservative simulation of VLSI circuits and systems

The deterministic nature of conservative simulation makes it possible to conduct an accurate trace-driven analysis of an existing sequential simulator in order to predict concurrency profiles and speedup bounds for several parallel implementations. This paper describes such an analysis carried out on a commercial VLSI digital circuit simulator with results based on real instance evaluation times at microsecond resolutions. The authors consider a central event queue based model with and without lookahead, as well as the distributed message passing model. The results help to answer the important questions, `Just how much concurrency is there in real commercial VLSI simulations?´ and `What type of machine would be best suited for a parallel implementation?´